Without limiting the scope of this invention, this background information is provided in the context of a specific problem to which the invention has application. Large counters for integrated and other circuits, which may also be referred to as high bit-count counters, are used as time-out counters or timers in power-management devices and the like. For example, time-out counters may be used to time a certain function in real time, e.g. screen display, disk drive, etc. However, to exhaustively test such counters in real time consumes an exorbitant amount of tester time. Typically such counters are tested by breaking the counter or divider or similar structure into segments and then test each smaller segment in parallel using a faster clock and observe the output of each of the segments. While this method accelerates the testability of the counters, it does not test the interface or connections between the segments. To fully test the prior art counters by also testing the interface, one would have to clock the counter its full amount in normal mode, and since the normal mode counter clock operates slower in normal mode than in test mode even more real time on the tester is consumed. However, even if the test mode operates at the same frequency as the normal mode, the need would still exist for testing all of the connections between the segments for exhaustive testing.
There thus remains a need to test not only each segment of the counter, but also the interfaces between segments and in a very brief portion of tester time.